50473681

9781546776345

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for  ASIC and FPGA Design
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  • ISBN-13: 9781546776345
  • ISBN: 1546776346
  • Edition: 1
  • Publication Date: 2017
  • Publisher: CreateSpace Independent Publishing Platform

AUTHOR

Stuart Sutherland

SUMMARY

Stuart Sutherland is the author of 'RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design', published 2017 under ISBN 9781546776345 and ISBN 1546776346.

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